Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements

Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate using static segmentation. these circuits a set $m$ contiguous bits (a segment bits) is extracted from each two notation="LaTeX">$n$ -bits operand, segments input small notation="LaTeX">$m\times m$ internal multiplier whose output suitably shifted obtain result. We both signed and unsigned multipliers, for latter propose new segmentation approach. also present simple effective correction techniques that can significantly reduce approximation error with reduced hardware costs. perform detailed comparison previously proposed considering implementation 28 nm technology. The shows segmented technique have desirable characteristic being on (or close to) Pareto-optimal frontier vs normalized mean distance relative trade-off plots. These therefore, promising candidates applications where their performance acceptable. This confirmed by obtained image processing classification applications.